1. Field of Invention
The invention relates to semiconductor-based electronic devices, and, more particularly, to the structure and fabrication of semiconductor-based substrates and electronic devices that include strained semiconductor layers.
2. Discussion of Related Art
Some advanced semiconductor-based devices include a semiconductor layer that is strained by application of a stress to provide improved performance of the devices. For example, metal-oxide-semiconductor (MOS) transistors having a channel formed in strained silicon or strained Si1-yGey formed on unstrained, or relaxed, Si1-xGex, can exhibit improved carrier mobility in comparison to traditional p-type MOS (PMOS) and n-type MOS (NMOS) transistors. Strained-layer MOS transistors can be formed on “virtual substrates,” which include a strained layer to provide compatibility with traditional silicon-based fabrication equipment and methods that were designed for use with conventional silicon wafers. A virtual substrate, in contrast, typically includes a strained silicon layer grown on a relaxed and/or graded Si1-xGex layer in turn grown on a silicon substrate.
To fabricate high-performance devices on these platforms, thin strained layers of semiconductors, such as Si, Ge, or Si1-yGey, can be grown on the relaxed Si1-xGex of a virtual substrate. The resulting biaxial tensile or compressive strain of the grown layers alters their carrier mobilities, enabling the fabrication of high-speed and/or low-power-consumption devices.
The relaxed Si1-xGex layer of a virtual substrate can in turn be prepared by, e.g., wafer bonding or direct epitaxy on Si, or by epitaxy on a graded SiGe buffer layer in which the lattice constant of the SiGe material has been increased gradually over the thickness of the buffer layer. The virtual substrate may also incorporate buried insulating layers, in the manner of a silicon-on-insulator (SOI) wafer. Deposition of a relaxed graded SiGe buffer layer enables engineering of the in-plane lattice constant of a relaxed Si1-xGex virtual substrate layer (and therefore the amount of strain the relaxed layer will induce in a strained silicon layer or other overlying layer), while also reducing the introduction of dislocations. The lattice constant of Si1-xGex is larger than that of Si, and is a function of the amount of Ge in the Si1-xGex alloy.
As a lattice-mismatched layer is deposited (such as a Si channel layer on a relaxed Si1-xGex layer), the deposited layer will initially be strained to match the in-plane lattice constant of the underlying silicon substrate. Above a certain critical thickness of the deposited layer, however, misfit dislocations typically form at the layer interface. The layer can then relax to its inherent lattice constant due to mismatch accommodation by the misfit dislocations.
A structure that incorporates a compressively strained SiGe layer in tandem with a tensilely strained Si layer can provide enhanced electron and hole mobilities. In this “dual channel layer” structure, electron transport typically occurs within a surface tensilely strained Si channel and hole transport typically occurs within both the compressively strained Si1-yGey layer below the Si layer and the Si layer at high gate overdrives.
Unfortunately, Si1-xGex-based substrates can increase the complexity of device fabrication. For example, the concentration profile of a Si-to-Si1-xGex interface can deteriorate due to diffusion that occurs during elevated temperature processing steps. Moreover, the hole wave function in a Si1-yGey dual channel layer can extend into an underlying oxide or relaxed SiGe layer. Thus, the desired hole mobility enhancement of a dual channel layer can be substantially less than theory predicts.